Specifications

ATAPI For Streaming Tape QIC-157 Rev B

Any Device that supports PIO Mode 3 or above shall support this field, and the value in word 68

shall not be less than 180. If the Device does not support this field, the Device shall return a value

of zero in this field.

4.1.8. Set Features

The Set Features command is used to set some interface timing and protocol modes. These modes

are set at initialization by many BIOSes. The content of the ATAPI Features Register indicates the

function to be performed.

Table 4-4 Contents of the Feature Register for Set Features Command

Bit

Byte

7 6 5 4 3 2 1 0

0 Feature

Set (1)

Clear (0)

Feature Number

Table 4-5 Set Feature Register Definitions

Feature Number Set Feature Commands Supported

01h Enable 8-bit data transfers No

02h Enable write cache No

03h Set transfer mode based on value in sector count register Mandatory

33h Disable retry No

44h Vendor unique length of ECC on read long/write long commands No

54h Set cache segments to sector count register value No

5Dh Enable Shared Interrupts No

55h Disable read look-ahead feature No

66h Disable reverting to power on defaults Mandatory

77h Disable ECC No

81h Disable 8-bit data transfers No

82h Disable write cache No

88h Enable ECC No

99h Enable retries No

AAh Enable read look-ahead feature No

ABh Set maximum prefetch using sector count register value No

BBh 4 bytes of ECC apply on read long/write long commands No

CCh Enable reverting to power on defaults Mandatory

DDh Disable Shared Interrupts No

If the value in the register is not supported or is invalid, the Device sets an Aborted Command error.

At power on, or after a hardware reset, the default mode is the same as that represented by values

greater than 80h.

4.1.8.1. Set Transfer Mode (03h)

The Host can choose the transfer mechanism by Set Transfer Mode and specifying a value in the

Sector Count Register. The upper 5 bits define the type of transfer and the low order 3 bits encode

the mode value. Since both PIO and DMA settings can be active simultaneously, the Device shall

maintain independent transfer mode settings for both PIO and DMA.