Specifications

ATAPI For Streaming Tape QIC-157 Rev B

Bit 10 IORDY can

be disabled

Is used to indicate a Device’s ability to enable or disable the use of

IORDY. If this bit is set to one, then the Device supports the disabling

of IORDY.

Bit 11 IORDY

Supported

This is used to help determine whether a Device supports IORDY. If

this bit is set to one, then the Device supports IORDY operation. If

this bit is zero then the Device may support IORDY (this ensures

backward compatibility.)

Bit 13 ATAPI

Reserved

Reserved for a Future ATAPI enhancement.

Bit 14 ATAPI

Reserved

Reserved for a Future ATAPI enhancement.

4.1.7.8. PIO Data Transfer Cycle Timing (Word 51)

The PIO transfer timing for each ATA Drive falls into categories that have unique parametric

timing specifications. To determine the proper Device timing category, compare the contents of this

field with the Cycle Time specified in Figure 6 of the ATA document in Appendix B. The value

returned in Bits 15-8 shall fall into one of the categories specified, and if it does not, then Mode 0

shall be used to serve as the default timing.

4.1.7.9. DMA Data Transfer Cycle Timing (Word 52)

The DMA transfer timing for each ATA Drive falls into categories that have unique parametric

timing specifications. To determine the proper Device timing category, compare the contents of this

field with the Cycle Time specified in Figures 8 and 9 of the ATA document in Appendix B. The

value returned in Bits 15-8 shall fall into one of the categories specified, and if it does not, then

Mode 0 shall be used to serve as the default timing.

4.1.7.10. Field Validity (Word 53)

Bit 0 = 0.

Bit 1 = 1; this bit guarantees that the fields contained in words 64-70 are valid.

4.1.7.11. Single Word DMA Transfer (Word 62)

The low order byte identifies by bit all of the modes that are supported, e.g., if Mode 0 is supported,

bit 0 is set. The high order byte contains a single bit set to indicate which mode is active, e.g., if

Mode 0 is active, bit 8 is set.

4.1.7.12. Multi Word DMA Transfer (Word 63)

The low order byte identifies by bit all of the modes that are supported, e.g., if Mode 0 is supported,

bit 0 is set. The high order byte contains a single bit set to indicate which mode is active, e.g., if

Word 0 is active, bit 8 is set.

4.1.7.13. Enhanced PIO Mode (Word 64)

Bits 7 through 0 of the word 64 of the Identify Device parameter information are defined as the

Advanced PIO Data Transfer Supported Field. This field is bit significant. Any number of bits may