Specifications

ATAPI For Streaming Tape QIC-157 Rev B

D7 D6 D5 D4 D3 D2 D1 D0

1 Reserved 1 DRV SAM LUN R/W

Figure 3-6 ATAPI Drive Select Register (ATA Drive / Head Select Register)

Bit 3-0 SAM LUN This field replaces the SCSI LUN within the CDB. This field shall be

set to zero.

Bit 4 DRV This bit selects either Device 0 (DRV=0) or 1 (DRV=1).

D7 D6 D5 D4 D3 D2 D1 D0

Reserved 1 SRST nIEN 0 Write

Figure 3-7 ATAPI Device Control Register (ATA Drive Control Register)

Bit 2 SRST This bit is the Software Reset. The ATAPI Device shall follow the

reset sequence for SRST defined in 3.3 ATAPI Implementation of

ATA SRST on page 17. There is also a new reset capability for

ATAPI Devices utilizing a Soft Reset command (see 3.2 ATAPI Soft

Reset Command and Protocol on page 17).

Bit 1 nIEN This bit enables/disables the interrupt to the Host. When nIEN=0 and

the Device is selected, INTRQ shall be enabled through a tri-state

buffer. When nIEN=1 or the Device is not selected, the INTRQ signal

shall be in a high impedance state