Specifications

ATAPI For Streaming Tape QIC-157 Rev B

Bit 6,5,4 Reserved Reserved for Tag Type.

Bit 3,2,1 Reserved Reserved for future enhancement.

Bit 0 DMA

(Optional)

Any data for the Command shall be transferred via the DMA

interface. Note this does not apply for the Command Packet.

D7 D6 D5 D4 D3 D2 D1 D0

Byte Count (Bits 0-7) R/W

Byte Count (Bits (8-15) R/W

Figure 3-4 ATAPI Byte Count Register (ATA Cylinder High/Low Register)

The Byte Count is used for PIO only; it is ignored for DMA operations.

Prior to the issuance of the Packet Command, the count shall be set to the maximum transfer size

per DRQ (at least 512 bytes).

When any data is to be transferred, the ATAPI device shall set the Byte Count to the amount of data

that the Host shall transfer and then issue a DRQ interrupt. The contents of this register shall not

change during the DRQ.

Implementor's Note: For commands which transfer less than 512 bytes, such as Inquiry or Mode

Sense, the Packet contains an allocation length, which may be used to limit the amount of data

transferred to the size of the buffer available in the Host.

D7 D6 D5 D4 D3 D2 D1 D0

Reserved IO CoD Read

Figure 3-5 ATAPI Interrupt Reason Register (ATA Sector Count Register)

Bit 0 CoD Command or Data. When this bit is zero then the information being

transferred is user data, when one then the data is Command.

Bit 1 IO Direction for the Information transfer, where in to the Host is

indicated by a value of one and out to the Device is zero.

IO DR

CoD

0 1 1 Command - Ready to Accept Command Packet Bytes

1 1 1 Message (Future) - Ready to Send Message data to Host

1 1 0 Data To Host- Send command parameter data (e.g. READ)

0 1 0 Data From Host - Receive command parameter data (e.g. WRITE)

1 0 1 Status - Register contains Completion Status