Specifications

ATAPI For Streaming Tape QIC-157 Rev B

D7 D6 D5 D4 D3 D2 D1 D0

BSY DRDY Reserved DSC DRQ CORR IDX CHECK Read

Figure 3-1 ATAPI Status Register (ATA Status Register)

DRDY, DSC, CORR and CHECK shall be valid at Completion Status of the command.

Bit 7 BSY Busy is set whenever the Device has access to the Command Block.

Bit 6 DRDY Indicates the Device is capable of responding to an ATA command.

Bit 5 Reserved

Bit 4 DSC Cleared during the actual execution of Media Access commands.

Devices shall hold BSY if ATAPI commands received while this bit

is cleared. While no unrecovered error is detected, this bit cleared

may also indicate buffer memory not ready to transfer up to

Continuous Transfer Limit. The ready state of the buffer memory

defaults to a write operation unless at an implied read position.

Bit 3 DRQ Data Request - Indicates that the Device is ready to transfer a word or

byte of data between the Host and the Device. Information in the

ATAPI Interrupt Reason shall also be valid during a Packet

Command when the DRQ is set.

Bit 2 CORR Indicates a Correctable Error occurred within data transferred.

Bit 1 IDX Reserved for future logical interrupt signal to identify source.

Bit 0 CHECK Indicates that an error occurred during execution of the previous

command. The Error Register contains the Sense Key and Code bits.

D7 D6 D5 D4 D3 D2 D1 D0

Sense Key MCR ABRT EOM ILI Read

Figure 3-2 ATAPI Error Register (ATA Error Register)

Bits 7-4 Sense Key The Sense Key is defined in Table 6-66 on page 89.

Bit 3 MCR Media Change Requested is used and defined as in the ATA Standard.

Bit 2 ABRT Aborted Command is used and defined as in the ATA Standard.

Bit 1 EOM End Of Media Detected.

Bit 0 ILI Illegal Length Indication.

D7 D6 D5 D4 D3 D2 D1 D0

Reserved Reserved for Tag Type Reserved DMA Write

Figure 3-3 ATAPI Feature Register (ATA Feature Register)

Bit 7 Reserved