Specifications

ATAPI For Streaming Tape QIC-157 Rev B
17
3.2. ATAPI Soft Reset Command and Protocol
ATA specifies a mandatory software reset capability because it provides a recovery mechanism
from a class of errors/problems that are recoverable in no other way. The current Drivers invoke
this feature at some point in their error recovery procedures today.
The ATA software reset mechanism, SRST, (bit 2 in the Drive Control Register) cannot be used for
ATAPI Devices, because resets issued by the ATAPI Driver would also reset any attached hard disk
and vice versa.
For a software reset to be useful it must be able to bring the Device’s microprocessor back from a
busy or hung condition to allow issuance of a diagnostic or some other command. Since the
microprocessor is the destination of the reset, we cannot depend on it as part of the reset path.
Therefore, ATAPI Soft Reset shall be detected/decoded by the interface controller circuitry and be
routed back to the microprocessor as a hardware signal. The Device shall ensure the format
integrity of any ongoing write operation before resetting.
Upon detection of the ATAPI Soft Reset command, the Device shall:
1. Set BSY when the command is decoded. When the reset sequence in the Device is complete the
Busy status shall be cleared. This will be the only status returned to the Host by the ATAPI Soft
Reset command.
2. Initialize the task file with the same information as after a Power On Reset. See section 3.1.1
Power On or Hardware Reset on page 16 for a description of the initialization sequence, except
for the DRV bit that shall remain unchanged.
3.3. ATAPI Implementation of ATA SRST
The ATA software reset mechanism, SRST, (bit 2 in the Drive Control Register) cannot be used for
ATAPI Devices, because resets issued by the ATAPI Driver would also reset any attached hard disk
and vice versa. To solve this ATAPI defines an ATAPI Soft Reset command using a reserved ATA
opcode that could be decoded by the interface controller hardware.
To maintain Master/Slave compatibility with ATA disk Drives and prevent detection of ATAPI
Devices by non ATAPI-aware BIOS, ATAPI Devices shall implement the following upon receipt of
an ATA SRST:
1. Follow the SRST Sequence defined in section 3.3.1 SRST Sequence on page 17, and not the
sequences shown in the ATA Specification.
2. Initialize the task file with Status = 00h, Error = 01h, Sector Count = 01h, Sector Number = 01h,
Cylinder Low = 14h, Cylinder High =EBh and Drive/Head = 00h.
3. Use the DSC bit to indicate completion of any command executing when SRST was detected.
4. Continue executing commands or play operations.
5. Leave Mode settings or Set Feature settings unchanged.
6. If an ATAPI Device detects SRST while DRQ=1 and the ATAPI Device is selected, then and
only then, shall an ATAPI Device abort a command in progress on receipt of an SRST.
3.3.1. SRST Sequence
This sequence does not match the ATA Standard but is used for ATAPI Devices.