Specifications

ATAPI For Streaming Tape QIC-157 Rev B
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2.12. Timing of Data and Status Transfer
BSY
I/O
CoD
DRQ
INTRQ
Byte Count
Read Status
Rd/Wr Data
5µs Maximum
Flow
Completion StatusData Transfer
2.13. Control Signal Timing Requirements and Relationships
The order that the signals change shall adhere to the following conditions:
1. Upon receiving the A0h ATAPI Packet Command the Device shall have BSY asserted until the
next Host access of the Status Register where the Device can guarantee that CoD=1 and IO=0.
2. The Device shall not assert DRQ until CoD and IO are valid for the command or data packet to
be transferred and the Device is ready to perform that transfer.
3. DRQ may be set before or after BSY has been deasserted.
4. The Device shall clear BSY and set DRQ within the time-out specified by the CMD DRQ Type.
See section 4.1.7.1 General Configuration Word (0), on page 25 for additional information.
5. Devices reporting CMD DRQ Type “Accelerated” shall de-assert DRQ within 5us of the last
word transferred for a command or data packet.
6. Devices reporting a CMD DRQ Type other than “Accelerated” shall de-assert DRQ, before
asserting INTRQ, following the last word transferred for a command or data packet.
Implementor's Note: Early ATAPI Devices reporting CMD DRQ Types other than “Accelerated”
may not be able to de-assert DRQ before the next INTRQ. Host systems should therefore wait until