Specifications

ATAPI For Streaming Tape QIC-157 Rev B

2.8. Flow of Packet Command with PIO Data Out from the Host

This class includes commands such as Mode Select, Write etc. Execution includes the transfer of

some known number of data bytes from the Host to the Device.

1. The Host Polls for BSY=0, DRQ=0 then initializes the task file by writing the required

parameters to the Features, Byte Count, and Drive/Head registers.

2. The Host writes the Packet Command code (A0h) to the Command Register.

3. The Device sets BSY, before the next system read of the status register, and prepares for

Command Packet transfer.

4. When the Device is ready to accept the Command Packet, the Device sets CoD and clears IO,

BSY prior to asserting DRQ. Some Devices will assert INTRQ following the assertion of DRQ.

See section 4.1.7.1 General Configuration Word (0), on page 25 for command packet DRQ

types and other related timing information.

5. After detecting DRQ, the Host writes the 12 bytes (6 words) of Command to the Data Register.

6. The Device(1) clears DRQ (when the 12

byte is written), (2) sets BSY, (3) reads Features and

Byte Count requested by the Host system, (4) prepares for data transfer.

7. When ready to transfer data, the Device:(1) sets the byte count (Cylinder High and Low

Registers) to the amount of data that the Device wishes to be sent , (2) clears IO and CoD, (3)

sets DRQ and clears BSY, (4) sets INTRQ. The Byte Count would normally be set to the

number of bytes requested by the contents of the register at the receipt of the command, but may

be any amount that the Device can accommodate in its buffers at this time.

8. After detecting INTRQ, the Host reads the DRQ bit in the Status Register to determine how it

shall proceed with the command. If DRQ= 0, then the Device has terminated the command. If

DRQ=1, then the Host shall write the data (number of bytes specified in the Cylinder High/Low

Registers) via the Data Register. In response to the Status Register being read, the Device

negates INTRQ for both cases.

9. The Device clears DRQ and sets BSY. If transfer of more data is required, the above sequence

is repeated from 7.

10. When the Device is ready to present the status, the Device places the completion status into the

Status Register, sets CoD, IO, DRDY and clears BSY, DRQ, prior to asserting INTRQ.

11. After detecting INTRQ & DRQ=0, the Host reads the Status Register and if necessary, the Error

The DRQ signal is used by the Device to indicate when it is ready to transfer data, and is cleared

after (during) the last byte of data to be transferred. This applies for Command Packet as well as

normal read/write data.

2.9. Flow of DMA Data Commands

This class includes commands such as Read, Write etc. Execution includes the transfer of some

unknown number of data bytes.

1. The Host Polls for BSY=0, DRQ=0 then initializes the task file by writing the required

parameters to the Features, Byte Count, and Drive/Head registers. The Host must also initialize

the DMA engine that will service the Device requests.