Specifications

ATAPI For Streaming Tape QIC-157 Rev B
8
upon receipt of any new ATAPI command. (See 2.15 ATAPI Command Protocol and DSC
Handling , page 5.)
3. If a command is executing when the Device is issued a SRST, the DSC bit shall be cleared with
the rest of the Status Register. The Host must issue ATAPI Identify or any packet command to
restore DSC operation.
2.7. Flow of Packet Command, PIO Data In to the Host
This class includes commands such as INQUIRY, READ etc. Execution includes the transfer of
some unknown number of data bytes from the Device to the Host. Note that ATAPI Identify is not a
packet command and uses ATA protocol (not ATAPI).
1. The Host Polls for BSY=0, DRQ=0 then initializes the task file by writing the required
parameters to the Features, Byte Count, and Drive/Head registers.
2. The Host writes the Packet Command code (A0h) to the Command Register.
3. The Device sets BSY, before the next system read of the status register, and prepares for
Command Packet transfer.
4. When the Device is ready to accept the Command Packet, the Device sets CoD and clears IO,
BSY prior to asserting DRQ. Some Devices will assert INTRQ following the assertion of DRQ.
See section 4.1.7.1 General Configuration Word (0), on page 25 for command packet DRQ
types and other related timing information. DRQ may be set before or after BSY has been de-
asserted; however, DRQ will not be visible to the Host until BSY=0.
5. After detecting DRQ, the Host writes the 12 bytes (6 words) of Command to the Data Register.
6. The Device(1) clears DRQ (when the 12
th
byte is written), (2) sets BSY, (3) reads Features and
Byte Count requested by the Host system, (4) prepares for data transfer.
7. When data is available, the Device: (1) places the byte count of the data available into the
Cylinder High and Low Registers, (2) sets IO and clears CoD, (3) sets DRQ and clears BSY, (4)
sets INTRQ.
8. After detecting INTRQ, the Host reads the DRQ bit in the Status Register to determine how it
shall proceed with the command. If DRQ= 0 then the Device has terminated the command. If
DRQ=1 then the Host shall read the data (number of bytes specified in the Cylinder High/Low
Registers) via the Data Register. In response to the Status Register being read, the Device
negates INTRQ for both cases.
9. The Device clears DRQ. If transfer of more data is required, the Device also sets BSY and the
above sequence is repeated from step 7.
10. When the Device is ready to present the status, the Device places the completion status into the
Status Register, sets CoD, IO, DRDY and clears BSY, DRQ, prior to asserting INTRQ.
11. After detecting INTRQ & DRQ=0, the Host reads the Status Register and, if necessary, the
Error Register for the command Completion Status.
The DRQ signal is used by the Device to indicate when it is ready to transfer data, and is cleared
after (during) the last byte of data to be transferred. This applies for Command Packet as well as
normal read/write data.