Specifications

 2012 Advanced Micro Devices, Inc.
Appendix B: Revision History
AMD SP5100 Register Programming Requirements
Page 74
September 11, 2008 2.07 • Replaced codename SB700S with SP5100 throughout the document.
• Added section 2.2: Unblocked SMI command port.
• Replaced previous section 2.9: Enabling IRQ1/12 Filtering with new section 2.10:
Interrupt Routing/Filtering.
• Removed previous section 2.28: Reverting USBCLK/14M_25M_48M_OSC Back
to A11 Mode.
• Added new section 2.29: SMBus Write Sequence.
• Updated section 4.12: Enabling AB and BIF Clock Gating. Changed setting for
ABCFG 0x54[24] to 0.
• Added section 6.16: MSI Feature in USB 2.0 Controller.
• Added section 6.17, EHCI Dynamic Clock Gating Feature.
• Added section 7.9: Disabling Aggressive Link Power Management.
•
Added section 7.10: Disabling SATA MSI Capability.
March 05, 2008 1.02 • Updated section 2.9: Enabling IRQ1/12 Filtering by updating the description for
register setting Smbus_PCI_config 0x62 [1:0].
•
Added section 6.15: EHCI Async Park Mode.
February 08, 2008 1.01 • Updated section 2.15: PCIe Native Mode by updating the descriptions and adding
registers to the PCIe Native Mode table.
• Added section 2.16: Hardware Monitor.
• Added section 2.17: Cir Interrupt Config.
• Added section 2.18: SM Pci Config.
• Added section 2.19: IMC Access Control
• Added section 2.20: CPU Reset.
• Added section 3: LPC Controller (bus-0, dev-20, fun-3).
• Updated section 4.15: SMI IO Write by changing the title of this section and by
updating the register description.
•
Added section 7.8: External SATA Ports Indication Registers.
May 07, 2007 1.00 • Initial OEM release.