Specifications

 2012 Advanced Micro Devices, Inc.
Appendix B: Revision History
AMD SP5100 Register Programming Requirements
Page 73
April 27, 2009 2.09 • Added ASIC revision A15 settings.
• General replacement of “A14” with “A14 and above”.
• Section 2.4 “C-State and VID/FID Change “: Updated description for PM_IO 0x8B.
• Section 2.16 ”PCIe

Native Mode”: Changed setting from 1 to 0 for PM_IO
0x84[1]; added suggested settings.
• Updated section 2.20 “IMC Access Control”
• Updated section 2.28 “Revision ID”.
• Added new section 2.34 “Software Clock Throttle Period”.
• Added new section 2.35 “Unconditional Shutdown”.
• Added new section 2.36 “Watchdog Timer Resolution”
• Updated section 4.16 “SMI IO Write”.
• Added new section 4.17 “Reset CPU on Sync Flood”.
• Added new section 4.18 “Enabling Posted Pass Non-Posted Downstream”.
• Added new section 4.19 “Enabling Posted Pass Non-Posted Upstream”.
• Added new section 4.20 “64-bit Non-posted Memory Write”.
• Updated new section 6.20 “Async Park Mode”.
• Added new section 6.24 “USB PID_Error_Checking”.
• Updated section 7.9 “Restoring SATA Registers after S3 Resume State” with 2
new settings for SATA Capability.
• Section 7.10 “External SATA Ports Indication Registers”: Added definition of
HCAP.SXS and Set Px.CMD.HPCP=0 for iSATA.
• Changed title of section 7.12 from “SATA MSI Capability” to “SATA MSI and D3
Power State Capability” and updated the section.
Feb 09, 2009 2.08 • Updated section 2.4, “C-State and VID/FID Change”: Distinguished StutterTime
for Family 10h and non-10h CPUs.
• Updated section 2.13, “Legacy DMA Pre-fetch Enhancement”: Added 2 new
settings.
• Updated section 2.16, “PCIE Native Mode”: Changed setting for PM_IO 0x84 [1]
from 0 to 1.
• Updated section 2.28, “Revision ID”: Corrected applicable ASIC revision to A12
and added Rev ID for A14.
• Added section 2.29, “Alternate Pin for 14 MHz Clock Input”.
• Added section 2.30, “Gevent2 as GPIO.”
• Added section 2.31, “PM_TURN_OFF_MSG during ASF Shutdown.”
• Added section 2.32, “SMBUS Block Write Filtering.”
• Added section 4.15, “Selecting LPC FRAME# Assertion Timing Power-up.”
• Updated section 4.5, “OHCI Prefectch Settings.”
• Updated section 6.1, “Enabling/Disabling OHCI and EHCI Controllers“ to correct
the ECHI Enable bit assignments.
• Updated section 6.10, “OHCI MSI Function Setting”: Corrected heading, and
corrected applicable ASIC Revision to “All Revs SP5100”
• Updated section 6.11: “EHCI Advance Asynchronous Enhancement”: Added A14
setting for enabling AEE function.
• Updated section 6.15, “EHCI Async Park Mode”: Added settings for enabling
async park mode for A14.
• Added section 6.17.1”Sample Code for the Workaround Described in SB7xx
Erratum #11 (ERN # ERA12011).
• Added sections 6.18-6.23.
• Updated section 7.1, “Enabling SATA.”
• Added section 7.2, “SATA Initialization.”
• Updated section 7.3, “Disabling SATA.”
• Added section 7.4, “SATA Power Saving.”
• Updated section 7.9, “Restoring SATA Registers after S3 Resume State”:
Updated applicable ASIC revisions for various register settings.
• Updated section 7.11, “Aggressive Link Power Management.”
• Updated section 7.12, “SATA MSI Capability”:
• Updated section 7.13, “Flash Controller” by adding a note to indicate FC is not
supported at platform level.
• Added section 7.15, “Disabling CCC (Command Completion Coalescing)
Support”:
• Updated section 9.1, “Disabling IDE MSI Capability”: Added setting for making
MSI capability visible.