Specifications
2012 Advanced Micro Devices, Inc.
Appendix B: Revision History
AMD SP5100 Register Programming Requirements
Page 72
Appendix B: Revision History
Date Revisions Description
July, 2012 3.02 • Added new section 6.22 Disable Async QH Cache.
Dec 22, 2011 3.01 • Updated section 2.4 C-State and VID/FID Change.
• Added new section 2.6 MTC1e and FID VID Setting.
•
Updated section 3.2 SPI Bus.
Nov, 2010 3.00 • Released as public version.
• Updated section 2.4 C-State and VID/FID Change: Added stutter time info for
different conditions.
• Modified/combined previous section 2.26 and 2.27 to remove support for ASF, but
indicating that SMBUS 1 can still be used as a master for SMBUS devices.
• Removed previous section 2.34 PM_TURN_OFF_MSG during ASF Shutdown.
• Merged previous section 2.42
Automatic Stutter Timer into section 2.5 Enable C1e
Stutter Timer and Limit Link Disconnect to < 20 ms.
• Added section 2.40 Programmable Interrupt Controller Arbitration.
• Added section 2.41 HPET MSI Setting.
• Added section 2.42 SMAF Matching Setting.
• Updated section 6.19 USB Controller DMA Read Delay Tolerant.
• Added Disable AHCI enhancement to section 7.2 SATA Initialization.
• Updated section 7.11 SATA MSI and D3 Power State Capability to include that
SATA MSI capability is not supported.
•
Update section 9.1 Disable Second IDE MSI Capability.
Sep 11, 2009 2.13 • Changed heading of section 2.36 from “SMBUS Write Sequence” to “SMBUS
Sequence” implying it now applies to both Read and Write. Also added
recommended time out of 1 ms or greater.
• Updated section 2.38 Unconditional Shutdown - clarified how to write to register
•
Added new section 2.43 LDT_PWRGD De-assertion with SLP_S3#.
July15, 2009 2.12 • Removed section 1.2 “Feature List”.
• Updated section 2.5 “Enable C1e Stutter Timer and Limit Link Disconnect to < 20
ms”
• Added section 2.6 “C1e Exit on Assertion of IDLE Exit# (for A15 Only)”.
• Added section 2.7 “Support for Entering C1e on HALT# Message (for a15 Only)”.
• Updated section 2.32 “Alternate Pin for 14 MHz Clock Input”.
• Added section 2.40 “Supporting IDLE_EXIT# from CPU”.
• Added section 2.41 “Supporting HALT Message to Generate C1e”.
• Added section 2.42 “Automatic Stutter Timer”.
• Removed previous section 7.12 “Flash Controller” and section 7.13 “Restoring FC
Registers after S3 Resume State”.
June 04, 2009 2.11 • Updated section 2.4 “C-State and VID/FID Change” to cover new generation CPU.
• Added new section 2.5 “Enable C1e Stutter Timer to Limit Link Disconnect to < 16
ms”
• Updated section 6.2 “USB Device Support to Wake Up System from S3/S4 State”.
• Moved section 6.17.1 “Sample Code for the Workaround Described in SB7xx
Erratum #11” into new Appendix A.
• Section 7.2 “SATA Initialization”: Added a new setting to the end of the table.
• Removed original section 7.4 “SATA Power Saving” since the block level power
saving function in SB7x0 is built-in and the register SMBUS_0xAC[13] is not for
this purpose.
• Updated section 7.9 “Internal and External SATA Ports Indication Registers”:
Added description of internal SATA (iSATA) port(s).
•
Added new Appendix A: Sample Codes for BIOS Workarounds.
April 29, 2009 2.10 • General edits.
•
Corrected section 7.4 “SATA Power Saving”