Specifications

 2012 Advanced Micro Devices, Inc.
IDE Controller (bus-0, dev-20, fun-01)
AMD SP5100 Register Programming Requirements
Page 64
9 IDE Controller (bus-0, dev-20, fun-01)
The SP5100 IDE controller supports single primary channel, even though resources of the
secondary IDE channel are allocated by the in-box driver from the Microsoft operating system.
Therefore the IDE programmable interface (IDE PCI config 0x09 bits [3:2]) is not recommended for
modification.
9.1 Disable Second IDE MSI Capability
ASIC Rev Register Settings Function/Comment
All Revs SP5100 IDE PCI_config 0x63 [5]=0 Hide MSI capability pointer.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
9.2 Enable IDE Data Bus DD7 Pull-Down Resistor
ASIC Rev Register Settings Function/Comment
All Revs SP5100 ACPI PMIO2 0xE5 [2] = 1
Enables IDE data bus DD7 internal pull down resistor at IO
pad. This PD should be enabled whenever IDE controller
enabled.
Note: If the FLASH controller is enabled or IDE DD& has
external PD, then this register should not be set.
Resume from S3 does not require to reset this bit.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC