Specifications

 2012 Advanced Micro Devices, Inc.
LPC (bus-0, dev-20, fun-03)
AMD SP5100 Register Programming Requirements
Page 63
8 LPC (bus-0, dev-20, fun-03)
8.1 Enabling/Disabling LPC Controller
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0x64 [20] = 1 (default) Enables the LPC controller.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
8.2 Parallel Port ECP Mode Support
ASIC Rev Register Settings Function/Comment
All Revs SP5100 If IO 0x378 & IO 0x778 as ECP (or
ECP+EPP) address port is used:
LPC_PCI_config 0x44 [0] = 1
LPC_PCI_config 0x44 [1] = 1
If IO 0x278 & IO 0x678 as ECP (or
ECP+EPP) address port is used:
LPC_PCI_config 0x44 [2] = 1
LPC_PCI_config 0x44 [3] = 1
If IO 0x3BC & IO 0x7BC as ECP (or
ECP+EPP) address port is used:
LPC_PCI_config 0x44 [4] = 1
LPC_PCI_config 0x44 [5] = 1
For the parallel port to support ECP mode, or ECP+EPP mode,
the SBIOS needs to allocate 2 base addresses for the parallel
port.
base_address_2 = base_address_1 + 0x400
Base_address_1 is controlled by register bit 0, or bit 2, or bit 4.
Base address_2 is controlled by register bit 1, or bit 3, or bit 5.
The SBIOS needs to enable both base addresses to properly
support ECP (or ECP+EPP) mode.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC