Specifications

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2012 Advanced Micro Devices, Inc.

SATA: dev-17, func-0

AMD SP5100 Register Programming Requirements

Page 62

7.11.3 Capability Pointer Settings

The following settings re-program the capability pointer to the recommended start of the

capabilities table of supported features (hide MSI, and if S1 is supported, hide D3 state capability

from driver/OS).

ASIC Rev Register Settings Function/Comment

All Revs SP5100 1. SATA_PCI_config 0x40 [0] = 1

2. SATA_PCI_config 0x61[7:0]=0x70

3. SATA_PCI_config 0x40 [0] = 0

D3 power state is visible. (If S1 is not supported)

MSI capability for SATA is hidden.

All Revs SP5100 1. SATA_PCI_config 0x40 [0] = 1

2. SATA_PCI_config 0x34[7:0]=0x70

3. SATA_PCI_config 0x40 [0] = 0

D3 power state is hidden. (If S1 is supported)

MSI capability for SATA is hidden.

SATA

USB

SMBUS

PATA

AC97

HD AUDIO

LPC

PCI

For register details, refer to

the sections check-marked

in the SP5100 Register

Reference Guide.

RTC

ACPI

PM REG

A-LINK

I/O REG

XIOAPIC

7.12 Disabling CCC (Command Completion Coalescing) Support

ASIC Rev Register Settings Function/Comment

All Revs SP5100 1. SATA_PCI_config 0x40 [0] = 1 Unlocks the configuration register so that HBA AHCI

Capabilities register can be modified.

2. SATA_BAR5 + 0xFC [19] = 0

Clearing this bit has the following effects:

Once this bit is cleared, SATA BAR5 + 0x00[7] will be 0

Command Completion Coalescing function will not be

supported.

3. SATA_PCI_config 0x40 [0] = 0 Clears the bit to lock configuration registers so that AHCI

HBA Capabilities register is read-only.