Specifications

 2012 Advanced Micro Devices, Inc.
SATA: dev-17, func-0
AMD SP5100 Register Programming Requirements
Page 61
Sequence to disable ALPM:
ASIC Rev Register Settings Function/Comment
All Revs SP5100 1. SATA_PCI_config 0x40 [0] = 1
Unlocks the configuration register so that HBA AHCI
Capabilities Register can be modified.
2. SATA_BAR5 + 0xFC [11] = 0
Clearing this bit has the following effects. The Support-
Aggressive-Link-Power-Management Capability is hidden
from software in AHCI HBA Capabilities Register. As a
result, software will not enable the HBA to aggressively
enter power-saving (Partial/Slumber) mode.
Once this bit is cleared, SATA BAR5 + 0x00[26] will be 0
3. SATA_PCI_config 0x40 [0]= 0
Clears the bit to lock configuration registers so that AHCI
HBA Capabilities register is read-only.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
7.11 SATA MSI and D3 Power State Capability
7.11.1 SATA MSI Settings
SATA controller does not support message based interrupts. The capability pointer offset needs
to be re-programmed from its default setting to prevent the driver from enabling this feature.
7.11.2 D3 Power State Settings
SATA controller does not support D3 Power State if S1 is supported. The capability pointer offset
needs to be re-programmed from its default setting to prevent the driver from enabling this
feature.