Specifications

 2012 Advanced Micro Devices, Inc.
SATA: dev-17, func-0
AMD SP5100 Register Programming Requirements
Page 60
7.9 Internal and External SATA Ports Indication Registers
The following registers need to be programmed for eSATA ports
ASIC Rev Register Settings Function/Comment
All Revs SP5100 For the ports which are configured as iSATA
ports.
1.PxCMD.ESP should leave as reset default
(logic 0).
2.PxCMD.HPCP should be cleared.
To clear the register, write:
Port0: SATA BAR5 + 0xF8[0]=0
Port1: SATA BAR5 + 0xF8[1]=0
Port2: SATA BAR5 + 0xF8[2]=0
Port3: SATA BAR5 + 0xF8[3]=0
Port4: SATA BAR5 + 0xF8[4]=0
Port5: SATA BAR5 + 0xF8[5]=0
For the ports which configured as eSATA.
1.PxCMD.ESP should be set.
To set the register, write:
Port0: SATA BAR5 + 0xF8[12]=1
Port1: SATA BAR5 + 0xF8[13]=1
Port2: SATA BAR5 + 0xF8[14]=1
Port3: SATA BAR5 + 0xF8[15]=1
Port4: SATA BAR5 + 0xF8[16]=1
Port5: SATA BAR5 + 0xF8[17]=1
2.PxCMD.HPCP should be cleared.
To clear the register, write:
Port0: SATA BAR5 + 0xF8[0]=0
Port1: SATA BAR5 + 0xF8[1]=0
Port2: SATA BAR5 + 0xF8[2]=0
Port3: SATA BAR5 + 0xF8[3]=0
Port4: SATA BAR5 + 0xF8[4]=0
Port5: SATA BAR5 + 0xF8[5]=0
3. If any of the ports is programmed as
External Port, HCAP.SXS should also be
set. To set the register, write:
SATA BAR5 + 0xFC[20]=1
PxCMD.ESP (External SATA Port) and PxCMD.HPCP
(Hot Plug Capable Port) registers should be programmed
to indicate if the port is used for External SATA and if it
requires hot Plug capability.
For iSATA (internal SATA) port(s), Px.CMD.HPCP and
Px.CMD.ESP should be logic 0.
To program these registers, SATA_PCI_config x40[0]
needs to be set. After the subclass is programmed,
SATA_PCI_config 0x40[0] needs to be reset.
For example, if port 0 was configured as eSATA, other
Ports are iSATA.
SATA BAR5 + F8[17:12]= 000001(b)
SATA BAR5 + F8[5:0] = 000000(b)
PxCMD.ESP bit is mutually exclusive with PxCMD.HPCP
bit in the same port.
In general:
If no E-SATA ports in system then HCAP.SXS=0 else
HCAP.SXS=1.
ESP HPCP
eSATA (signal only connector) 1 0
iSATA 0 0
PxCMD ESP located at:
SATA BAR5+ port offset + 0x18[21]
PxCMD HPCP located at:
SATA BAR5+ port offset + 0x18[18]
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
7.10 Aggressive Link Power Management
ALPM controls the HIPM functionality. The ALPM bit is also used by the SATA driver to enable
HIPM and DIPM. Customers should check with the drive vendor to confirm if the SATA device
being used is compatible and functional with HIPM and DIPM capability before enabling the ALPM.
HIPM and DIPM are supported in the SP5100. If the customer requires HIPM / DIPM support and
gets confirmation from the drive vendors that the drivers they are supporting will enable HIPM, then
this feature can be enabled. The following registers need to be programmed to disable the ALPM.
Note: If the ALPM needs to be enabled, the following sequence should NOT be programmed.