Specifications

 2012 Advanced Micro Devices, Inc.
SATA: dev-17, func-0
AMD SP5100 Register Programming Requirements
Page 59
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
7.8 Restoring SATA Registers after S3 Resume State
The following registers need to be restored by the SBIOS after S3 resume for the SATA controller.
ASIC Rev Register Settings Function/Comment
All Revs SP5100 SATA_PCI_config 0x09 [7:0]
SATA_PCI_config 0x0A [7:0]
Programmable interface and Subclass code. To program
the subclass code register, SATA_PCI_config x40[0]
needs to be set. After the subclass is programmed,
SATA_PCI_config 0x40[0] needs to be reset.
SATA_PCI_config 0x44 [0] Enables the Watch-dog timer for the all ports.
SP5100 A12 SATA_PCI_config 0x40 [29] Disables the testing/enhancement mode.
SP5100 A12 SATA_PCI_config 0x48 [24] Disables the testing/enhancement mode.
SP5100 A12 SATA_PCI_config 0x48 [21] Disables the testing/enhancement mode.
SP5100 A14 and
above
SATA_PCI_config 0x40 [29]
SATA_PCI_config 0x48 [24]
SATA_PCI_config 0x48 [21]
SATA_PCI_config 0x48 [15:9]
Smbus_PCI_config 0xAC [13]
Enables the testing/enhancement mode.
All Revs SP5100 SATA_PCI_config 0x86 [15:0]
SATA_PCI_config 0x88 [24:0]
SATA_PCI_config 0x8C [24:0]
SATA_PCI_config 0x90 [24:0]
SATA_PCI_config 0x94 [24:0]
SATA_PCI_config 0x98 [24:0]
SATA_PCI_config 0x9C [24:0]
SATA_PCI_config 0xA0 [15:0]
SATA_PCI_config 0xA2 [15:0]
SATA_PCI_config 0xA4 [15:0]
SATA_PCI_config 0xA6 [15:0]
SATA_PCI_config 0xA8 [15:0]
SATA_PCI_config 0xAA [15:0]
SATA PHY setting.
All Revs SP5100
SATA_PCI_config 0x34 [7:0]
SATA_PCI_config 0x61 [7:0]
SATA Capability
All Revs SP5100 SATA BAR5 + 0xF8[17:0] SATA ports indication registers.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC