Specifications

 2012 Advanced Micro Devices, Inc.
SATA: dev-17, func-0
AMD SP5100 Register Programming Requirements
Page 57
7.6 SATA PHY Programming Sequence
The SBIOS needs to program the SATA controllers in the following sequence. Performing this
procedure gives enough time for the SATA controllers to correctly complete SATA drive detection.
The SBIOS needs to do the same procedure after the system resumes back from the S3 state.
Note: This will be added once the silicon comes back for PHY fine tune value.
ASIC Rev Register Settings Function/Comment
All Revs SP5100 1. SATA_PCI_config 0x86 [15:0] = 0x2C00 SATA PHY global setting.
2. SATA_PCI_config 0x88 [31:0] =
0x01B48017
SATA_PCI_config 0x8C [31:0]=
0x01B48019
SATA_PCI_config 0x90 [31:0] =
0x01B48016
SATA_PCI_config 0x94 [31:0] =
0x01B48016
SATA_PCI_config 0x98 [31:0] =
0x01B48016
SATA_PCI_config 0x9C [31:0] =
0x01B48016
SATA GENI PHY ports setting, pre-emphasis setting, and
GENII PHY setting enable setup for port [0~5] This setting
is for the Travelly board. Since its port0 and port1are
eSATA ports, PCI_config 0x88 and 0x8C have different
settings than the rest of the ports. For non-eSATA
port, the
setting should be 0x01B48016. For the Shinner board,
SATA_PCI_config 0x88/8C/90/94/98/9C [31:0] =
0x01B48016.
3.SATA_PCI_config 0xA0 [15:0] = 0xA09A
SATA_PCI_config 0xA2 [15:0] = 0xA09F
SATA_PCI_config 0xA4 [15:0] = 0xA07A
SATA_PCI_config 0xA6 [15:0] = 0xA07A
SATA_PCI_config 0xA8 [15:0] = 0xA07A
SATA_PCI_config 0xAA [15:0] = 0xA07A
SATA GEN II PHY port setting for port [0~5]. This setting is
for the Travelly board. Since its por
t0 and port1 are eSATA
ports, PCI_config 0xA0 and 0xA2 have different settings
than the rest of the ports. For non-esata port, the setting
should be 0xA07A. For the Shinner board,
SATA_PCI_config 0xA0/A2/A4/A6/A8/AA [15:0] = 0xA07A.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC