Specifications
2012 Advanced Micro Devices, Inc.
SATA: dev-17, func-0
AMD SP5100 Register Programming Requirements
Page 53
7 SATA: dev-17, func-0
7.1 Enabling SATA
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0xAC [8] = 1 Enables the SATA controller.
7.2 SATA Initialization
ASIC Rev Register Settings Function/Comment
All Revs SP5100
Smbus_PCI_config 0xAC [28:26]
SATA interrupt mapping to PCI interrupt pins. These bits
should be programmed by the BIOS for correct assignment
of SATA interrupt mapping/
SATA_PCI_config 0x40 [0] = 0 This bit needs to be cleared to convert the subclass code
register to read-only. Refer to section 7.6 for the SATA
subclass programming sequence.
SATA_PCI_config 0x44 [0] = 1 Enables the SATA watchdog timer register prior to the SATA
BIOS post. See Note.
SP5100 A12
SATA_PCI_config 0x40 [29] = 1
SATA_PCI_config 0x48 [24] = 1
Set bit 29 and 24 for A12.
Bit 29 and 24 on A14 are cleared on power-up. These bits
can be set to 0 or not programmed.
Clearing bit 29 and 24 will enable the hardware to send the
byte count updates during the AHCI mode PIO transfers to
meet the SATA Specification. On A12, the byte count
updates are not sent and the bit should be left as 0. The
feature is required only for certain vendor-specific
diagnostics that check the updated byte counts status. There
is no functional impact as the OS drivers do not check for the
byte count during the PIO transfer but only after the transfer
is completed. On both A12 and A14, the byte count is
updated after the transfer is completed, even without this
feature enabled.
SP5100 A14
and
above
SATA_PCI_config 0x40 [29] = 0
SATA_PCI_config 0x48 [24] = 0
Restore the registers on the following conditions:
ASIC Revision
Restore after
A12
A14, A15
S3
Yes
Yes
S4
Yes
No
Warm boot
Yes
No
SP5100 A12 SATA_PCI_config 0x48 [21] = 1
Set bit 21 for A12
Bit 21 on A14 and above is cleared on power up. This bit
can be set to 0 or not programmed.
Clearing the bit will enable the compatibility feature. It
allows the SATA controller to be able to handle the case
where the device might follow COMWAKE with one Align
instead of multiple Aligns as required normally. This is not
a normal case for the devices, but was observed on one of
the SATA devices during qualification.
SP5100 A14 and
above
SATA_PCI_config 0x48 [21] = 0
Restore the registers on the following conditions
ASIC Revision
Restore after
A12
A14, A15
S3
Yes
Yes
S4
Yes
No
Warm boot
Yes
No