Specifications

 2012 Advanced Micro Devices, Inc.
USB – OHCI & EHCI controllers (bus-0, dev-18/19, fun-00 ~02/
bus-0, dev-20, fun-05)
AMD SP5100 Register Programming Requirements
Page 50
6.20 Async Park Mode
ASIC Rev Register Settings Function/Comment
SP5100 All Revs EHCI PCI_Config 0x50[23] = 1 Async Park Mode function.
For normal operation, the APM function should be disabled
by setting the bit in both EHCI controllers:
Bus-0 Dev-18 Func-2 and Bus 0 Dev-19 Func-2
If EHCI APM is enabled, some USB card reader devices
may not work properly. The USB controller used on these
devices may not be able to handle the short delay time
between the data packets.
SP5100 A14 and
above
EHCI PCI_Config 0x50[2] = 0 Disable Async Park Extra Mode function.
This is hardware default; BIOS should not program the
register.
This bit should be disabled in USB1 EHCI controller only.
Bus-0 Dev-18 Func-2.
The bit in Bus-0 Dev-19 Func-2 is reserved and should not
be programmed.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
6.21 Resume Reset Timing
ASIC Rev Register Settings Function/Comment
SP5100 A14 and
above
OHCI 0 PCI_Config 0x50[17] = 1
Set this bit to 1 on revision A14. This register setting is
required to enable the Reset Timing feature. This feature will
resolve the issue listed in A12 Errata (item #7).
The bit must be programmed in both of the OHCI0
controllers:
Bus-0 Dev-18 Func- 0 and Bus 0 Dev-19 Func-0
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
X
RTC ACPI PM REG A-LINK I/O REG XIOAPIC
6.22 Disable Async QH Cache
ASIC Rev
Register Settings
Function/Comment
SP5100 A15 EHCI PCI Config 0x50[25] = 1 Disable Async QH/QTD Cache
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
X
RTC ACPI PM REG A-LINK I/O REG XIOAPIC