Specifications

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2012 Advanced Micro Devices, Inc.

USB – OHCI & EHCI controllers (bus-0, dev-18/19, fun-00 ~02/

bus-0, dev-20, fun-05)

AMD SP5100 Register Programming Requirements

Page 46

6.8 Adjusting USB 2.0 Ports Driving Strength

ASIC Rev Register Settings Function/Comment

All Revs SP5100

Step 1:

EHCI_BAR 0xB4 [2:0] = “HSADJ”

EHCI_BAR 0xB4[12] = 0

EHCI_BAR 0xB4 [16:13] = “port#”

Step 2:

EHCI_BAR 0xB4[12] = 1

Adjusts the USB2.0 ports driving strength.

HSADJ to set the driving strength value

VLoadB to load the value to the PHY for selected port

The selected port#

The SBIOS can repeat step-1 for those ports with less

margin on HS eye diagram.

Set to ‘1’ to lock PHY UTMI Control interface.

Note:

1. Different board designs may require different settings for different ports depending on trace length and routing.

2. Only apply the setting to the ports that have longer USB trace lengths (> 12 inches) to the connector, and if the eye

diagram margin is not enough. There is no need to apply these setting to the ports with shorter trace lengths or

close to the USB connectors.

3. EHCI_BAR 0xB4 = EHCI_EOR 0x94 (UTMI Control Register)

4. EHCI_BAR 0xB4[2:0] (HSADJ)

“000” = -10% , “001” = -5%, “100” = 0%, “101” = +5%, “110” = +10%

EHCI_BAR 0xB4[16:13] (port#)

“0000” = port0 , “0001” = port1, …… “0101” = port5, 0110 ~ 1110: reserved.

SATA

USB

SMBUS

PATA

AC97

HD AUDIO

LPC

PCI

For register details refer to

the sections check-marked

in the SP5100 Register

Reference Guide

RTC

ACPI

PM REG

A-LINK

I/O REG

XIOAPIC

6.9 In and Out Data Packet FIFO Threshold