Specifications

 2012 Advanced Micro Devices, Inc.
USB – OHCI & EHCI controllers (bus-0, dev-18/19, fun-00 ~02/
bus-0, dev-20, fun-05)
AMD SP5100 Register Programming Requirements
Page 45
6.5 USB Reset Sequence
ASIC Rev Register Settings Function/Comment
All Revs SP5100 PM_IO 0x65 [4] = 1 Enables the USB controller to get reset by any software that
generates a PCIRst# condition. However, this bit should be
cleared before a software generated reset condition occurs
during S3 resume so the USB controller will not lose the
connection status during the S3 resume procedure.
The software generated PCIRst# conditions include
Keyboard Reset, or write to the IO-CF9 register.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
6.6 USB Advanced Sleep Control
ASIC Rev Register Settings Function/Comment
All Revs SP5100 PM_IO 0x95 [2:0] = 110b Enables the USB EHCI controller advance sleep mode
function to improve power saving.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
6.7 USB 48 MHz Clock Source Settings
ASIC Rev Register Settings Function/Comment
All Revs SP5100 PM_IO 0xD0 [0] = 0 (default)
PM_IO 0xBD [4] = 1
PM_IO 0xBD [6] = 1 (optional)
Enables PLL “CG_PLL2” to generate 48Mhz clock internally.
Enables the internal 48Mhz as the clock source to
USBPHY
Enables the IO pad “USBCLK/14M_25M_48M” as clock
output pad that it can be used for on board devices. This is
optional (depending on board requirement).
Note: To use internal 48 MHz clock, the 100 MHz PCIe

clock sourced from the external clock chip must not have spread
spectrum enabled.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC