Specifications

 2012 Advanced Micro Devices, Inc.
USB – OHCI & EHCI controllers (bus-0, dev-18/19, fun-00 ~02/
bus-0, dev-20, fun-05)
AMD SP5100 Register Programming Requirements
Page 43
6 USB – OHCI & EHCI controllers (bus-0, dev-18/19, fun-00
~02/ bus-0, dev-20, fun-05)
Please note the following information for this section:
• EHCI BAR address = EHCI_PCI_config 0x10[31:8]
• EHCI_EOR is the EHCI operation register = EHCI_BAR + 0x20
• The device list for all USB Controllers is as follows:
Device List Function/Comment
Bus-0, dev-18, fun-0 USB1, OHCI0
Bus-0, dev-18, fun-1 USB1, OHCI1
Bus-0, dev-18, fun-1 USB1, EHCI
Bus-0, dev-19, fun-0 USB2, OHCI0
Bus-0, dev-19, fun-1 USB2, OHCI1
Bus-0, dev-19, fun-1 USB2, EHCI
Bus-0, dev-20, fun-5 USB3, OHCI
6.1 Enabling/Disabling OHCI and EHCI Controllers
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0x68 [2] = 1 (default) Enables the USB1 (bus-0, dev-18) EHCI controller.
Smbus_PCI_config 0x68 [0] = 1 (default) Enables the USB1 (bus-0, dev-18) OHCI controller 1
(OHCI0).
Smbus_PCI_config 0x68 [1] = 1 (default) Enables the USB1 (bus-0, dev-18) OHCI controller 2
(OHCI1).
Smbus_PCI_config 0x68 [6] = 1 (default) Enables the USB2 (bus-0, dev-19) EHCI controller.
Smbus_PCI_config 0x68 [4] = 1 (default) Enables the USB2 (bus-0, dev-19) OHCI controller 1
(OHCI0).
Smbus_PCI_config 0x68 [5] = 1 (default) Enables the USB2 (bus-0, dev-19) OHCI controller 2
(OHCI1).
Smbus_PCI_config 0x68 [7] = 1 (default) Enables the USB3 (bus-0, dev-20, fun-5) OHCI controller.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC