Specifications

 2012 Advanced Micro Devices, Inc.
PCIB (PCI-bridge, bus-0, dev-20, fun-04)
AMD SP5100 Register Programming Requirements
Page 41
5.11 Enabling Additional Optional PCI Clock (PCICLK5)
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x64 [8] = 1 This only applies when PCICLK5/PCIREQ5#/PCIGNT5#
are enabled: When this bit is set, PCICLK5, PCIREQ#5,
and PCIGNT5# are enabled for PCI use. Since PCICLK5 is
not enabled by default (the clock is off), the PCI device
which uses this clock may not see the system reset during
power-up. To correct this, the BIOS should write to PCIB
config 3Eh, bit [6] to assert the additional PCI reset so the
device will see a proper reset, as well as to provide the
time for its internal PLL to lock. The recommended
duration time is at least a few milliseconds.
Note: These three pins are enabled as a group, therefore,
care should be taken to make sure they are used properly.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
5.12 Enabling One-Prefetch-Channel Mode
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x64 [20] = 0x1 Enables One-Prefetch-Channel Mode.
Note: This setting is mandatory.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
5.13 Disabling PCIB MSI Capability
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x40 [3] = 0x0 (default) Disables MSI capability.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC