Specifications

 2012 Advanced Micro Devices, Inc.
PCIB (PCI-bridge, bus-0, dev-20, fun-04)
AMD SP5100 Register Programming Requirements
Page 40
5.7 Enabling Idle To Gnt# Check
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x4B [0] = 1 (default) When enabled, the PCI arbiter checks for the Bus Idle
before asserting GNT#.
Note: This setting is recommended.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
5.8 GNT# Timing Adjustment
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x64 [12] = 1 (default) Adjusts the GNT# de-assertion time.
Note: This setting is recommended.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
5.9 Enabling Fast Back to Back Retry
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x48 [2] = 1 (default) Enables Fast Back to Back transactions support.
Note: This setting is recommended
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
5.10 Enabling Lock Operation
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x48 [3] = 1 (default) This bit should be set to 1 when PCI configuration space
PCIB_PCI config 0x40 [2] = 1 for the proper operation of
the PCI LOCK# function.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC