Specifications

 2012 Advanced Micro Devices, Inc.
TOC
AMD SP5100 Register Programming Requirements
Page 4
2.37 Watchdog Timer Resolution ....................................................................................................... 26
2.38 Supporting IDLE_EXIT# from CPU .......................................................................................... 27
2.39 Supporting HALT Message to Generate C1e .............................................................................. 27
2.40 LDT_PWRGD De-assertion with SLP_S3# ............................................................................... 28
2.41 Programmable Interrupt Controller Arbitration .......................................................................... 28
2.42 HPET MSI Setting ...................................................................................................................... 28
2.43 SMAF Matching Setting ............................................................................................................. 29
3 LPC Controller (bus-0, dev-20, fun-3) ................................................................ 30
3.1 IO / Mem Decoding ..................................................................................................................... 30
3.2 SPI Bus ........................................................................................................................................ 30
4 A-Link Express Settings - Indirect I/O Access ................................................. 31
4.1 Defining AB_REG_BAR ............................................................................................................ 31
4.2 Clearing AB_INDX ..................................................................................................................... 31
4.3 Enabling Upstream DMA Access ................................................................................................ 32
4.4 IDE/PCIB Prefetch Settings ........................................................................................................ 32
4.5 OHCI Prefetch Settings ............................................................................................................... 32
4.6 B-Link Client’s Credit Variable Settings for the Downstream Arbitration Equation ................. 33
4.7 Enabling Additional Address Bits Checking in Downstream Register Programming ................ 33
4.8 Set B-Link Prefetch Mode ........................................................................................................... 33
4.9 Enabling Detection of Upstream Interrupts ................................................................................. 34
4.10 Enabling Downstream Posted Transactions to Pass Non-Posted Transactions ........................... 34
4.11 Programming Cycle Delay for AB and BIF Clock Gating.......................................................... 34
4.12 Enabling AB and BIF Clock Gating ............................................................................................ 35
4.13 Enabling AB Int_Arbiter Enhancement ...................................................................................... 35
4.14 Enabling Requester ID ................................................................................................................ 35
4.15 Selecting the LPC FRAME# Assertion Timing on Power-up ..................................................... 35
4.16 SMI IO Write .............................................................................................................................. 36
4.17 Reset CPU on Sync Flood ........................................................................................................... 36
4.18 Enabling Posted Pass Non-Posted Downstream ......................................................................... 36
4.19 Enabling Posted Pass Non-Posted Upstream .............................................................................. 37
4.20 64 bit Non-Posted Memory Write Support ................................................................................. 37
5 PCIB (PCI-bridge, bus-0, dev-20, fun-04) ........................................................... 38
5.1 Enabling PCI-bridge Subtractive Decode ................................................................................... 38
5.2 PCI-bridge Upstream Dual Address Window ............................................................................. 38
5.3 PCI Bus 64-byte DMA Read Access
.......................................................................................... 38
5.4 PCI Bus DMA Write Cacheline Alignment ................................................................................ 39
5.5 Master Latency Timer ................................................................................................................. 39
5.6 DMA Read Command Match ..................................................................................................... 39
5.7 Enabling Idle To Gnt# Check ...................................................................................................... 40
5.8 GNT# Timing Adjustment .......................................................................................................... 40
5.9 Enabling Fast Back to Back Retry .............................................................................................. 40