Specifications

 2012 Advanced Micro Devices, Inc.
PCIB (PCI-bridge, bus-0, dev-20, fun-04)
AMD SP5100 Register Programming Requirements
Page 39
5.4 PCI Bus DMA Write Cacheline Alignment
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x40 [1] = 1 (default) Enables the PCIB writes to be cacheline aligned.
The size of the writes will be set in the Cacheline Register
(PCIB_PCI_config 0x4B[4:0]). Refer to section 5.3 for more
information.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
5.5 Master Latency Timer
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x0D = 0x40 (default)
PCIB_PCI_config 0x1B = 0x40 (default)
Enables the PCIB to retain ownership of the bus on the
Primary side and on the Secondary side when GNT# is de-
asserted.
Note: This setting is mandatory.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
5.6 DMA Read Command Match
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x4B[6] = 1 (default) Enables the command matching checking function on
“Memory Read” & “Memory Read Line” commands.
Some PCI devices may change the “Memory read
command” to “Memory read line” command before the data
is completed. This bit enables the command matching
checking inside the PCIB to work with this kind of device.
Note: This setting is mandatory.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC