Specifications

 2012 Advanced Micro Devices, Inc.
PCIB (PCI-bridge, bus-0, dev-20, fun-04)
AMD SP5100 Register Programming Requirements
Page 38
5 PCIB (PCI-bridge, bus-0, dev-20, fun-04)
5.1 Enabling PCI-bridge Subtractive Decode
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x40 [5] = 1
PCIB_PCI_config 0x4B [7]= 1
Enables the PCI-bridge subtractive decode.
This setting is strongly recommended since it supports some
legacy PCI add-on cards.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
5.2 PCI-bridge Upstream Dual Address Window
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x50 [0] = 1 PCI-bridge upstream dual address window.
This setting is applicable if the system memory is more than
4GB, and the PCI devices can support dual address access.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
5.3 PCI Bus 64-byte DMA Read Access
ASIC REV Register Settings Function/Comment
All Revs SP5100 PCIB_PCI_config 0x4B [4] = 1 (default) PCI bus 64-byte DMA read access.
Enhances the PCI bus DMA performance.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC