Specifications

 2012 Advanced Micro Devices, Inc.
A-Link Express Settings - Indirect I/O Access
AMD SP5100 Register Programming Requirements
Page 36
4.16 SMI IO Write
ASIC Rev Register Settings Function/Comment
SP5100 A12
ABCFG 0x9C[8] = 1
IO write and SMI ordering enhancement enabled
SP5100 A14 and
above
ABCFG 0x9C[8] = 0 IO write and SMI ordering enhancement disabled
SP5100 A15 ABCFG 0x90[21] = 1
ABCFG 0x9C[5] = 1
ABCFG 0x9C[9] = 1
ABCFG 0x9C[15] = 1
SMI ordering enhancement enabled
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
4.17 Reset CPU on Sync Flood
ASIC Rev Register Settings Function/Comment
SP5100 All Revs
ABCFG 0x10050[2] = 1 Enable SP5100 to initiate a CPU Reset on sync_flood.
This bit should be enabled in very early post.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
4.18 Enabling Posted Pass Non-Posted Downstream
ASIC Rev Register Settings Function/Comment
SP5100 A15 AX_INDXC 0x2[9] = 1
ABCFG 0x9C[6] = 1
ABCFG 0x9C[7] = 1
ABCFG 0x9C[10] = 1
ABCFG 0x9C[11] = 1
ABCFG 0x9C[12] = 1
ABCFG 0x9C[13] = 1
ABCFG 0x9C[14] = 1
ABCFG 0x1009C [4] = 1
ABCFG 0x1009C [5] = 1
ABCFG 0x10090 [9] = 1
ABCFG 0x10090 [10] = 1
ABCFG 0x10090 [11] = 1
ABCFG 0x10090 [12] = 1
Posted pass non-posted downstream direction feature
enable.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X