Specifications

 2012 Advanced Micro Devices, Inc.
A-Link Express Settings - Indirect I/O Access
AMD SP5100 Register Programming Requirements
Page 35
4.12 Enabling AB and BIF Clock Gating
ASIC Rev Register Settings Function/Comment
All Revs SP5100 ABCFG 0x54[24] = 0
ABCFG 0x10054[24] = 1
ABCFG 0x98[11:8] = 0x7
Enables the AB and BIF clock-gating logic.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
4.13 Enabling AB Int_Arbiter Enhancement
ASIC Rev Register Settings Function/Comment
All Revs SP5100 ABCFG 0x10054[15:0] = 0x07FF Enables the A-Link int_arbiter enhancement to allow A-
Link bandwidth to be used more efficiently
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
4.14 Enabling Requester ID
ASIC Rev Register Settings Function/Comment
All Revs SP5100
ABCFG 0x98[16] = 1
Enables the requester ID for upstream traffic
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
4.15 Selecting the LPC FRAME# Assertion Timing on Power-up
ASIC Rev Register Settings Function/Comment
SP5100 A14 and
above
Lpc_PCI_config 0x8C [17] = 0
Set the bit to 0 for revision A14 to assert LFRAME# signals
on SB Power good assertion.
Setting the bit to 1 will configure LPC to assert the
LFRAME# signal on de-assertion of SLP_S3# signal on
power up.
This register bit is not supported on A12 and should not be
programmed by the BIOS.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
x
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC