Specifications

 2012 Advanced Micro Devices, Inc.
A-Link Express Settings - Indirect I/O Access
AMD SP5100 Register Programming Requirements
Page 34
4.9 Enabling Detection of Upstream Interrupts
ASIC Rev Register Settings Function/Comment
All Revs SP5100 ABCFG 0x94 [20] = 1
ABCFG 0x94 [19:0] = CPU interrupt delivery
address [39:20].
Enables A-Link Express logic to detect upstream interrupts
for the purposes of system management.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
4.10 Enabling Downstream Posted Transactions to Pass Non-
Posted Transactions
ASIC Rev Register Settings Function/Comment
All Revs SP5100 ABCFG 0x10090 [8] = 1 Enables downstream posted transactions to pass non-
posted transactions.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
4.11 Programming Cycle Delay for AB and BIF Clock Gating
ASIC Rev Register Settings Function/Comment
All Revs SP5100 ABCFG 0x54 [23:16] = 0x4
ABCFG 0x10054 [23:16] = 0x4
ABCFG 0x98 [15:12] = 0x4
Program # of cycles to delay before gating AB and BIF
clocks after idle condition.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X