Specifications

 2012 Advanced Micro Devices, Inc.
A-Link Express Settings - Indirect I/O Access
AMD SP5100 Register Programming Requirements
Page 32
4.3 Enabling Upstream DMA Access
ASIC Rev Register Settings Function/Comment
All Revs SP5100 AXCFG: 0x04 [2] = 1 Enables the SP5100 to issue memory read/write requests in
the upstream direction.
Programming Sequence:
OUT AB_INDX, 0x80000004 // Load AB_INDX with pointer to AXCFG:0x04
IN AB_DATA, TMP // Read COMMAND register (AXCFG:0x04)
OR TMP, 0x00000004 // Set bit 4
OUT AB_DATA, TMP // Set BUS_MASTER_EN
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
4.4 IDE/PCIB Prefetch Settings
ASIC Rev Register Settings Function/Comment
All Revs SP5100 IDE prefetch
ABCFG 0x10060 [17] = 1
ABCFG 0x10064 [17] = 1
PCIB prefetch
ABCFG 0x10060 [20] = 1
ABCFG 0x10064 [20] = 1
The settings on AB control the IDE and PCIB prefetch. For
all revisions the pre-fetch needs to be enabled for
performance enhancement.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
4.5 OHCI Prefetch Settings
ASIC Rev Register Settings Function/Comment
All Revs SP5100 ABCFG 0x80 [0] = 1
This register in AB controls the USB OHCI controller
prefetch used for enhancing performance of ISO out
devices.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X