Specifications

 2012 Advanced Micro Devices, Inc.
A-Link Express Settings - Indirect I/O Access
AMD SP5100 Register Programming Requirements
Page 31
4 A-Link Express Settings - Indirect I/O Access
4.1 Defining AB_REG_BAR
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0xF0 [31:0] =
AB_REG_BAR
Defines the AB I/O base address.
Refer to AMD SP5100 Register Reference Guide, chapter 4:
A-Link Express/A-Link Bridge Registers for more
information.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
4.2 Clearing AB_INDX
The programming procedure for the ABCFG registers, as specified in the register reference
guide, is to first load AB_INDX with a register’s RegSpace and RegAddr; and then access the
specified register through AB_DATA. The example below demonstrates how to read
ABCFG:10058h:
OUT AB_INDX, 0xC0010058 // Set AB_INDX RegSpace=11 RegAddr=0x10058
IN AB_DATA, TMP
For certain revisions of the chip, the ABCFG registers, with an address of 0x100NN (where ‘N’ is
any hexadecimal number), require an extra programming step. This required step is defined in
the following table:
ASIC Rev Register Settings Function/Comment
All Revs SP5100 AB_INDX = 0x00000000 Clears AB_INDX after reading or writing an ABCFG
register with an address 0x100NN.
Example Programming Sequence:
OUT AB_INDX, 0xC00100NN // Load AB_INDX with pointer to ABCFG:0x100NN
IN AB_DATA, TMP // Read ABCFG 0x100NN
OUT AB_INDX, 0x00000000 // Clear AB_INDX
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X