Specifications

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2012 Advanced Micro Devices, Inc.

LPC Controller (bus-0, dev-20, fun-3)

AMD SP5100 Register Programming Requirements

Page 30

3 LPC Controller (bus-0, dev-20, fun-3)

3.1 IO / Mem Decoding

ASIC Rev Register Settings Function/Comment

All Revs SP5100 Lpc_PCI_config 0xBB[7] = 1

Lpc_PCI_config 0xBB[6] = 1

Lpc_PCI_config 0xBB[3] = 1

These bits are required to be set for LPC PCI slave

interface.

SATA

USB

SMBUS

PATA

AC97

HD AUDIO

LPC

PCI

For register details refer to

the sections check-marked

in the SP5100 Register

Reference Guide

RTC

ACPI

PM REG

A-LINK

I/O REG

XIOAPIC

3.2 SPI Bus

ASIC Rev Register Settings Function/Comment

All Revs SP5100

Lpc_PCI_config 0xBB[5] = 1

Set to 1 to allow SPI Op code to execute even though it is

now strapped as LPC Rom. Some BIOS code may want to

send SPI opcodes to check if SMI Rom is present. If the

system configuration is set for LPC, then the SPI opcode will

not be passed to SPI if this bit is not set.

Spi_mmio 0x00[28] = 1

Allows the software to read the status number of the SPI

read cycles completed – 1. Eliminates the last count.

Lpc_PCI_config 0xBB[0] = 1

Set to 1 to improve SPI read performance.

The bit should be set after programming the I/O modes and

SPI speed.