Specifications
2012 Advanced Micro Devices, Inc.
TOC
AMD SP5100 Register Programming Requirements
Page 3
Table of Contents
1 Introduction ................................................................................................................ 7
1.1 About This Manual ........................................................................................................................ 7
1.2 AMD SP5100 Block Diagram ....................................................................................................... 8
1.3 Register Reference Information .................................................................................................... 9
2 ACPI/SMBUS Controller (bus-0, dev-20, fun-0)................................................ 10
2.1 Enabling Legacy Interrupt ........................................................................................................... 10
2.2 Unblocked SMI Command Port .................................................................................................. 10
2.3 WakeIO Base Address ................................................................................................................ 10
2.4 C-State and VID/FID Change ..................................................................................................... 10
2.5 Enable C1e Stutter Timer and Limit Link Disconnect to < 20 ms ............................................. 13
2.6 MTC1e and FID VID Setting ...................................................................................................... 14
2.7 C1e Exit on Assertion of IDLE Exit# (for A15 Only) ................................................................ 14
2.8 Support for Entering C1e on HALT# Message (for A15 Only) .................................................. 14
2.9 Enabling Non-Posted Memory Write .......................................................................................... 15
2.10 Therm Trip Settings .................................................................................................................... 15
2.11 Sx State Settings .......................................................................................................................... 15
2.12 Output Drive Strength Settings ................................................................................................... 16
2.13 SUS_STAT# Enhancement ......................................................................................................... 16
2.14 Interrupt Routing/Filtering .......................................................................................................... 16
2.15 IO Trap Settings .......................................................................................................................... 17
2.16 Enabling ACPI Registers ............................................................................................................ 17
2.17 Legacy DMA Prefetch Enhancement .......................................................................................... 18
2.18 USB Set BM_STS ....................................................................................................................... 18
2.19 Enabling Spread Spectrum .......................................................................................................... 18
2.20 PCIe
Native Mode ..................................................................................................................... 19
2.21 Hardware Monitor ....................................................................................................................... 19
2.22 Cir Interrupt Config ..................................................................................................................... 20
2.23 SMBUS PCI Config .................................................................................................................... 20
2.24 IMC Access Control .................................................................................................................... 20
2.25 CPU Reset ................................................................................................................................... 21
2.26 Disabling Legacy USB Fast SMI# .............................................................................................. 21
2.27 SMBUS1 Programming Sequence .............................................................................................. 21
2.28 ACPI System Clock Setting ........................................................................................................ 23
2.29 Integrated Pull-up and Pull-down Settings .................................................................................. 23
2.30 Revision ID .................................................................................................................................
23
2.31 Alternate Pin for 14 MHz Clock Input ........................................................................................ 24
2.32 Gevent5 as GPIO ......................................................................................................................... 24
2.33 SMBUS Block Write Filtering .................................................................................................... 25
2.34 SMBUS Sequence ....................................................................................................................... 25
2.35 Software Clock Throttle Period ................................................................................................... 25
2.36 Unconditional Shutdown ............................................................................................................. 26