Specifications

 2012 Advanced Micro Devices, Inc.
ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
AMD SP5100 Register Programming Requirements
Page 28
2.40 LDT_PWRGD De-assertion with SLP_S3#
ASIC Rev Register Settings Function/Comment
SP5100 A15 Smbus_PCI_config 0x41 [3]=1 Set this bit to 1 to force LDT_PWRGD to be de-asserted at
the same time as SLP_S3#.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
x
RTC
ACPI
PM_REG
A-LINK
I/O REG
XIOAPIC
2.41 Programmable Interrupt Controller Arbitration
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0xAE [6]=1 Set this bit to 1 to allow the arbiter proper operation in
cases where both the PIC and APIC are enabled.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
x
RTC
ACPI
PM_REG
A-LINK
I/O REG
XIOAPIC
2.42 HPET MSI Setting
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0x40 [31:29]= 000b Program these register bits ONLY if the following are true
in the platform configuration:
1. Legacy Floppy Drive interface supported
2. Legacy FIR device supported
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
x
RTC
ACPI
PM_REG
A-LINK
I/O REG
XIOAPIC