Specifications

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2012 Advanced Micro Devices, Inc.

ACPI/SMBUS Controller (bus-0, dev-20, fun-0)

AMD SP5100 Register Programming Requirements

Page 27

2.38 Supporting IDLE_EXIT# from CPU

ASIC Rev Register Settings Function/Comment

The following register should be programmed to support IDLE_EXIT# from CPU to wake C1e state

SP5100 revision

A14 and above

SMBUS PCI 0x64[5]=1

PMIO 0x61[2]=1

PMIO_0x9A[5:4]=11

Enable BM_STS# pin

Enable BM_STS# to break C1e

Enable automatic BM_STS clearing upon C1e entry

SATA

USB

SMBUS

PATA

AC97

HD AUDIO

LPC

PCI

For register details, refer to

the sections check-marked

in the SP5100 Register

Reference Guide.

RTC

ACPI

PM_REG

A-LINK

I/O REG

XIOAPIC

This part of logic borrows the existing legacy ACPI BM_STS and BM_RLD bits as a mechanism to break out from C1e

under a non-OS controlled C3 state. Under this scheme, the logic will automatically clears the BM_STS bit whenever it

enters C1e state. Whenever BM_REQ#/IDLE_EXIT# is detected, it will cause the BM_STS bit to be set and thereby

causing the C state logic to exit. BIOS should clear the BM_STS bit on every post.

2.39 Supporting HALT Message to Generate C1e

ASIC Rev Register Settings Function/Comment

The following register should be programmed to support HALT message to C1e function

SP5100 A14 and

above

PMIO 0xBB[7]=1

PMIO_0xC9[4]=1

PMIO 0xC9[3:0] = Number of Halt Enter

messages to trigger C1e

Enable HALT message to C1e function

Enable counting of HALT message

Setting number of HALT messages to generate C1e