Specifications

 2012 Advanced Micro Devices, Inc.
ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
AMD SP5100 Register Programming Requirements
Page 25
2.33 SMBUS Block Write Filtering
ASIC Rev Register Settings Function/Comment
SP5100 A14 and
above
Smbus_PCI_config 0x38 [7]=0 Enable SMBUS filtering circuit. Setting this bit to 0 to
enable SMBUS filtering (1194).
THIS FEATURE WILL RESOLVE THE ISSUE DESCRIBED IN
REVISION
A12 ERRATA ITEM # 13.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
x
RTC
ACPI
PM_REG
A-LINK
I/O REG
XIOAPIC
2.34 SMBUS Sequence
The following programming sequence should be followed when reading or writing to the
SMBUS 0:
1. read HostBusy bit
2. if not zero
if time out (recommended time out == 1ms or greater)
set kill bit
go back step 1.
else
go to step 3
3. read SlaveBusy
4. if not zero
if time out
set reset bit
go back step 3.
else
go to step 5
5. clear HostStatus register, program Slave Address register/Command register/ Data0/Data1/Data
6. read HostControl register
7. write HostControl register to start the transaction.
8. wait HostBusy bit to be 1
9. wait HostBusy bit to be 0
10.wait one SMBUS clock period.
11. wait HostBusy bit to 0.
2.35 Software Clock Throttle Period
ASIC Rev Register Settings Function/Comment
All Revs SP5100
PMIO 0x68[7:6] = 10
Set AcpiThrotPeriod field in MiscEnable68 to 244 µS
(Hardware default is set to 15 µS)