Specifications

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2012 Advanced Micro Devices, Inc.

ACPI/SMBUS Controller (bus-0, dev-20, fun-0)

AMD SP5100 Register Programming Requirements

Page 24

2.31 Alternate Pin for 14 MHz Clock Input

ASIC Rev Register Settings Function/Comment

The following change is required for SP5100 revision A14 and above and if the 14 MHz clock is connected to the SB on to

25M_48M_66M_OSC. This reference clock is required to resolve the revision A12 Errata item #5 in hardware instead of

using the BIOS workaround. If external 14 MHz clock is not used on SP5100 rev A14 and above, then the BIOS

workaround described in erratum #5 should be implemented.

SP5100 A14 and

above

PMIO 0xD4[6] = 1

Program this register to ‘1’ if the system supports 14.318

MHz reference clock connected to 25M_48M_66M_OSC.

This reference clock is required to resolve the revision A12

Errata item #5 in hardware instead of using the BIOS

workaround.

This register bit is not supported on A12 and should not be

programmed by the BIOS.

SATA

USB

SMBUS

PATA

AC97

HD AUDIO

LPC

PCI

For register details, refer to

the sections check-marked

in the SP5100 Register

Reference Guide.

RTC

ACPI

PM_REG

A-LINK

I/O REG

XIOAPIC

2.32 Gevent5 as GPIO

ASIC Rev Register Settings Function/Comment

SP5100 A14 and

above

PMIO 0xD7[2] = 1

This bit should be programmed if the Gevent5 needs to be

used as for GPIO function on revision A14.

Revision A12 does not support GPIO function on the

GEVENT pin.

Programming this register for A14 will make this pin on

A14 function as GPIO. (Note that the GEVENT pin still

needs to be programmed for GPIO as any other pins. The

programming of this bit is in addition to the normal

programming procedure of GPIO/ GEVENT pins.)

If this bit is cleared, the function of this pin is same as in

revision A12. The power up default of this bit is ‘0’.

0 ( default ) : Disable

1 : Enable