Specifications

 2012 Advanced Micro Devices, Inc.
ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
AMD SP5100 Register Programming Requirements
Page 22
ASFSMbusIoBase- RW - 16 bits - [PCI_Reg: 58h]
Field Name
Bits
Default
Description
Reserved
3:1
000b
ASFSMBase
15:4
FFFh
ASF SM bus controller Io base address
• Step 3: Disable Legacy Sensor support by programming bit[6] of ASF I/O 0Dh to 1
SlaveMisc- RW - 8 bits - [ASF_IO: 0Dh]
Field Name
Bits
Default
Description
SlavePECError
0
0b
RO
0: No PEC error
1: PEC error
SlaveBusCollision
1
0b
RO
0: No BusCollision
1: BusCollision happens
SlaveDevError
2
0b
RO
0: Expected response
1: Unexpected response
WrongSP 3 0b RO
0: No SP error
1: No SP when turn to read
Reserved 4 0b
SuspendSlave
5
0b
RW
Write 1 to Suspend (stop) ASF Slave state machine
KillSlave
6
0b
RW
Write 1 to reset Slave ASF Slave state machine
LegacySensorEn
7
0b
RW
0: Disable Legacy Sensor
1: Enable Legacy Sensor
• Step 4: Enable PEC if SMBUS device supports PEC:
HostControl – RW - 8 bits - [ASF_IO: 02h]
Field Name
Bits
Default
Description
Reserved
0
0b
KillHost 1 0b 0: Enable SM master
1: Reset SM master
Protocol 4:2 000b 000: Quick
001: Byte
010: Byte Data
011: Word Data
100: Process call
101: Block
PECAppend
5
0b
0: No PEC append
1: Automatic PEC append. ASF HC calculates CRC code and append
to the tail of the data packets.
Start
6
0b
WO:
0: Always read 0 on reads
1: Writing 1 to initiate the command
PECEnable
7
0b
0: PEC disable
1: PEC enable, enable CRC checking when ASF HC presents
as SM master and SM slave.