Specifications

ManualsBrandsMicrosoft ManualsIP PhoneSP5100/S



2012 Advanced Micro Devices, Inc.

ACPI/SMBUS Controller (bus-0, dev-20, fun-0)

AMD SP5100 Register Programming Requirements

Page 21

2.25 CPU Reset

ASIC Rev Register Settings Function/Comment

All Revs SP5100 PM_IO 0xB2[2] = 1 Enables the CPU Reset timing option defined in PM

to be changed.

SATA

USB

SMBUS

PATA

AC97

HD AUDIO

LPC

PCI

For register details refer to

the sections check-marked

in the SP5100 Register

Reference Guide

RTC

ACPI

PM REG

A-LINK

I/O REG

XIOAPIC

2.26 Disabling Legacy USB Fast SMI#

ASIC Rev Register Settings Function/Comment

All Revs SP5100 Smbus_PCI_config 0x62 [5] = 1 Legacy USB can request SMI# to be sent out early before

IO completion. Some applications may have problems with

this feature. The BIOS should set this bit to 1 to disable the

feature.

SATA

USB

SMBUS

PATA

AC97

HD AUDIO

LPC

PCI

For register details refer to

the sections check-marked

in the SP5100 Register

Reference Guide

RTC

ACPI

PM REG

A-LINK

I/O REG

XIOAPIC

2.27 SMBUS1 Programming Sequence

ASF SMBUS 1 interface incorporates ASF and SMBUS1 controllers. ASF features (capability of using

ACPI services by ASF master) are not supported on SP5100. However, the SMBUS1 controller can be

used as a generic SMBUS interface with SMBUS1 controller operating as master to communicate to

SMBUS slave devices that need to be on S5 power domain. The ASF slave controller in SP5100 is

disabled but some registers belonging to ASF controller will need to be programmed to support SMBUS1

controller in Master mode.

• Step 1: Set the base address of ASF IO space by programming bits [15:4] of Sm cfg space reg

58h:

ASFSMbusIoBase- RW - 16 bits - [PCI_Reg: 58h]

Field Name

Bits

Default

Description

ASFSMBusEnable

0: Disable ASF controller

1: Enable ASF controller

Reserved

3:1

000b

ASFSMBase 15:4 FFFh ASF SM bus controller Io base address

• Step 2: Enable the ASF controller by programming bit[0] of Sm cfg space reg 58h: