Specifications

 2012 Advanced Micro Devices, Inc.
ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
AMD SP5100 Register Programming Requirements
Page 20
2.22 Cir Interrupt Config
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0xE1[6] Set to 1 to treat Cir interrupt as level signal; otherwise it
is edge.trigger:
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
2.23 SMBUS PCI Config
ASIC Rev Register Settings Function/Comment
A11 and A12 Smbus_PCI_config 0xE1[0] = 1 Forces Smbus controller to be enabled all the time, even if
Io/Mem decoding bit is set to 0.
A11 and A12
Smbus_PCI_config 0xE1[1]
Mmio decoding required setting
All Revs SP5100 Smbus_PCI_config 0xE1[2] Set to 1 to enable Io port 60h read/write SMi trapping and
Io port 64h write Smi trapping.
Smbus_PCI_config 0xE1[3] = 1
Required for INTA message decoding.
Smbus_PCI_config 0xE1[4] = 1
Smbus0 busy bit enhancement
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
2.24 IMC Access Control
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0xE1[7] = 1
Smbus_PCI_config 0xAF[1] = 0
Required for proper function of the IMC shared access.
The following register should only be programmed if IMC is enabled
Smbus_PCI_config 0xE1[5] = 1 Required for proper function of the IMC shared access.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC