Specifications
2012 Advanced Micro Devices, Inc.
ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
AMD SP5100 Register Programming Requirements
Page 17
All Revs SP5100
USB HC(bus0, dev 19, fun 0) MMio+160h
Set to 0000_0000h when USB legacy support is disabled in
internal USB host controller side. SW has to make sure that
the USB Hc memory decoding is enabled in PCI
configuration space command register.
USB HC(bus0, dev 20, fun 5) MMio+160h Set to 0000_0000h
when USB legacy support is disabled in
internal USB host controller side. SW has to make sure that
the USB Hc memory decoding is enabled in PCI
configuration space command register
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
2.15 IO Trap Settings
ASIC Rev Register Settings Function/Comment
All Revs SP5100
PM_IO 0x14 ~ 0x1B, 0xA0 ~ 0xA7 Programmable address ranges for IO trap.
PM_IO 0x1C ~ 0x1D, 0xA8 ~ 0xA9
IO trap enable/status registers.
1. ABCFG 0x10090 [16] = 1
2. PM_IO 0x14 ~ 0x1D or 0xA0 ~ 0xA9
ABCFG 0x10090 [16]
= 1 ensures the SMI# message to be
sent before the IO command is completed.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
X
2.16 Enabling ACPI Registers
ASIC Rev Register Settings Function/Comment
All Revs SP5100 1. Assign the IO base address for the
following ACPI registers:
- AcpiPm1EvtBlk = PM_IO 0x20, 0x21
- AcpiPm1CntBlk = PM_IO 0x22, 0x23
- AcpiPmTmrBlk = PM_IO 0x24, 0x25
- CpuControl = PM_IO 0x26, 0x27
- AcpiGpe0Blk = PM_IO 0x28, 0x29
- AcpiSmiCmd = PM_IO 0x2A, 0x2B
- AcpiPmaCntBlk = PM_IO 0x2C, 0x2D
2. Set AcpiDecodeEnable
- PM_IO 0x0E[3] = 1
The BIOS needs to a
ssign the IO base address for each of
the ACPI registers before enabling the ACPI decode. The
IO base addresses are defined in PM_IO 0x20 ~ 0x2F
registers.
Note 1: The PM_IO 0x20 ~ 0x2F registers are undefined
upon the first system power up and may therefore contain
random values. If the BIOS enables the ACPI decode
without assigning the proper IO base addresses for the
ACPI registers, the SB may decode incorrect IO addresses
and cause unexpected system behavior.
Note 2: The PM_IO 0x2E/2F registers must be
programmed with a valid I/O address. The recommended
address is using the AcpiSmiCmd + 8. Leaving this register
to a default of 0 will cause a conflict with legacy DMA.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X