Specifications

 2012 Advanced Micro Devices, Inc.
ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
AMD SP5100 Register Programming Requirements
Page 16
2.12 Output Drive Strength Settings
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0xC0 [29:0]
Setting TBD
These register bits configure the drive strength of each
individual bus.
Refer to the AMD SP5100 Register Reference Guide,
SMBUS section describing the PCI config C0h for the
recommended driving strength values.
Note: For more detail please refer to the AMD SP5100 Register Reference Guide.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
X
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
2.13 SUS_STAT# Enhancement
ASIC Rev Register Settings Function/Comment
All Revs SP5100 PM_IO 0x7C[5] 1 = Enable SUS_STAT# enhancement.
0 = Disable SUS_STAT# enhancement.
If enabled SUS_STAT# assertion will be extended until
after the SB has fully resumed from the S3/4/5 state.
Note: This is a precautionary measure to suppress a glitch on the CKE pin for some early NB revisions on the P4 platform.
Enable it only if the NB requires.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
2.14 Interrupt Routing/Filtering
ASIC Rev Register Settings Function/Comment
All Revs SP5100
Smbus_PCI_config 0x62 [1:0]
The filtering for IRQ1 and IRQ12 should be enabled only
when USB legacy support is enabled in internal USB host
controller side.
Smbus_PCI_config 0x67 [7]
The bit should be set to 1 only when USB legacy support is
enabled in internal USB host controller side.. By setting to 1
IRQ1/IRQ12 to PIC and IoApic controller comes from USB
legacy block.
Smbus_PCI_config 0x64 [13] = 1
Delay back to back interrupts to the CPU. The h
ardware will
delay an interrupt for approximately 500ns if there is a
pending interrupt. Some applications in PIC mode may not
be able to handle back to back interrupts in a short time
period. Enabling this bit will prevent the application from
encountering back to back interrupts.
USB HC(bus0, dev 18, fun 0) MMio+160h
Set to 0000_0000h
when USB legacy support is disabled in
internal USB host controller side. SW has to make sure that
the USB Hc memory decoding is enabled in PCIi
configuration space command register.