Specifications

2012 Advanced Micro Devices, Inc.
ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
Page 15
2.9 Enabling Non-Posted Memory Write
ASIC Rev Register Settings Function/Comment
All Revs SP5100 AXINDC:0x10 [9] = 1 Enables non-posted memory write.
Programming Sequence:
OUT AB_INDX, 0x00000030 // Load AB_INDX with pointer to AX_INDXC
OUT AB_DATA, 0x00000010 // Write 0x10 to AX_INDXC
OUT AB_INDX, 0x00000034 // Load AB_INDX with pointer to AX_DATAC
IN AB_DATA, TMP // Read PCIE_CTL register (AXINDC:0x10)
OR TMP, 0x00000200 // Set bit 9
OUT AB_DATA, TMP // Set PCIE_HT_NP_MEM_WRITE.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
2.10 Therm Trip Settings
ASIC Rev Register Settings Function/Comment
All Revs SP5100 PM_IO 0x68 [3] 0 = Disable the ThermTrip function on GEvent#2 pin.
1 = Enable the ThermTrip function on GEvent#2 pin.
PM_IO 0x55 [0] = 1 (default) With this bit set to 1, the ThermTrip function once activated
will shutdown the system.
PM_IO 0x67 [6:5] These two bits are used to set the polarity of the ThermTrip
and the TempCaut signals.
Default = 00 (this means that the signals are active low).
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X
2.11 Sx State Settings
ASIC Rev Register Settings Function/Comment
All Revs SP5100 PM_IO 0x65 [7] = 0 (default) Use 8us clock for delays in the S-state resume timing
sequence.
PM_IO 0x68 [2] = 1 (default) Delay the APIC interrupt to the CPU until the system has
fully resumed from the S-state.
Note: These 2 registers need to be set correctly for the S-state to work properly. Otherwise the system may hang during
resume from the S-state.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
X