Specifications

 2012 Advanced Micro Devices, Inc.
ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
AMD SP5100 Register Programming Requirements
Page 14
2.6 MTC1e and FID VID Setting
ASIC Rev Register Settings Function/Comment
The following registers should be programmed only if FIDVID is enabled in conjunction with MTC1e
SP5100 All Revs
PM_IO 0x9A [2] = 0
K8CpopUp is disabled
PM_IO 0x7C 0] = 0
EnableBreak is disabled
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
RTC
ACPI
PM_REG
A-LINK
I/O REG
XIOAPIC
x
2.7 C1e Exit on Assertion of IDLE Exit# (for A15 Only)
ASIC Rev Register Settings Function/Comment
The following registers should be programmed to support the C1e exit when Sp5100 IDLE_EXIT# is connected to
BM_REQ# as break event
SP5100 rev A15.
SMBUS PCI 0x64[5]=1
Enable BMREQ# pin to the C state logic
PMIO_61[2]=1
Monitor BM_STS pin from NB and BM from SB
PMIO_9A[4]=1
BM_STS cause SB to wakeup from C3
PMIO_9A[5]=1
Clear BM_STS when system enters C3
SMBUS PCI 0x64[4]=0
Force IDLE_EXIT# to set BM_STS and wakes from C3.
SMBUS PCI 0x64[5]=1
SMBUS PCI config 0x64 should be restored after resume from S3 and S4.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
x
RTC
ACPI
PM_REG
A-LINK
I/O REG
XIOAPIC
x
2.8 Support for Entering C1e on HALT# Message (for A15 Only)
ASIC Rev Register Settings Function/Comment
The following registers should be programmed to support the CE1e with HALT# message.
SP5100 rev A15.
PMIO_BB[7]=1
Count HALT number and go into C3 automatically
PMIO_C9[4]=1
Monitor number of HALT messages
PMIO_C9[3:0]=1
number of HALTS to enter C1e
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
x
RTC
ACPI
PM_REG
A-LINK
I/O REG
XIOAPIC
x