Specifications

 2012 Advanced Micro Devices, Inc.
ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
AMD SP5100 Register Programming Requirements
Page 13
2.5 Enable C1e Stutter Timer and Limit Link Disconnect
to < 20 ms
ASIC Rev Register Settings Function/Comment
Stutter timer settings
The following settings will program the stutter timer settings. There are two different values that need to be applied based
on the condition listed below.
Case 1
The following registers should be programmed only when Platform BIOS detects the CPUs listed below:
• Family 10h with LS2 mode capability enabled:
Model=6 && Stepping=2 II Model=(4I5|6) && Stepping >=3 || Model=(8|9) && Stepping >= 1 || Model
Ah
Case 2
Any CPU that does NOT meet the requirement in Case 1
SP5100 Rev A14
and above
PM_IO 0xCB [5] =1
AutoStutterTimerEn.
Set to 1 to enable.
PM_IO_0XCB[6] =1
Auto Stutter Timer time base select.
1 = millisecond
0 = 2 microseconds (set to 1 to select millisecond
increments)
SMBUS PCI config 0x5C[7] = 1
Monitor C3 state if set to 1.
Case 1
SMBUS PCI config 0x5C[22:16] = 14h
This register defines the timer value to trigger in 1
millisecond increments. (Set to 20 ms)
Case 2
SMBUS PCI config 0x5C[22:16] = 10h
This register defines the timer value to trigger in 1
millisecond increments. (Set to 16 ms)
SMBUS PCI config 0x5C should be restored after resume from S3 and S4.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details, refer to
the sections check-marked
in the SP5100 Register
Reference Guide.
x
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
x
This part of logic borrows another function within SB to automatically stutter the C1e state when LDTSTOP# has been
asserted continuously for a period of time defined by SmartVolt time. Originally this logic was for monitoring system activity,
by setting AutoStutterTimerEn PMIO_CB[5], this logic becomes a timer to stutter the C1e.