Specifications
2012 Advanced Micro Devices, Inc.
ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
AMD SP5100 Register Programming Requirements
Page 11
ASIC Rev Register Settings Function/Comment
All Revs SP5100 PM_IO 0x9A [4] = 1 For system with dual core CPU, set this bit to 1 and
BM_STS will cause C3 to wakeup regardless of BM_RLD.
All Revs SP5100
PM_IO 0x8F [5] = 1
Ignores BM_STS_SET message from NB
All Revs SP5100 +
RS4x0 ASIC family
of NB
PM_IO 0x8F [4] = 1 The SB will monitor BmReq# for C3 pop-up. The SB will
de-assert LDTSTP# when BmReq# is active.
All Revs SP5100 +
RS690 ASIC family
of NB
PM_IO 0x8F [4] = 0 The SB will not monitor BmReq# for C3 pop-up. The SB
will de-assert LDTSTP# when AllowLdtStop is not active.
BmReq# activity is combined on AllowLdtStop in the
RS690 ASIC family of NB.
Stutter time: The following setting is for Stutter time (minimum
time LDTSTP# is asserted before entering C3 state). There
are two settings that apply to different cases as listed below.
Case 1:
The following registers should be programmed only when Platform BIOS detects the CPUs listed below:
• Family 10h with LS2 mode capability enabled:
Model=(8|9) && Stepping >= 1 || Model Ah OR for any CPU that has the HT link speed set to 200 MHz.
• Family 15h with LS2 mode capability enabled:
Model= (00-0Fh) && C32r1 package || Model= (00-0Fh) && G34r1 package
Case 2:
Any CPU that does not meet the requirements set in Case 1.
All Revs SP5100
PM_IO 0x8B = 0x0A
Case 1:
StutterTime = 0x0A for minimum LDTSTP# assertion
duration of 10 us in C3.
PM_IO 0x8B = 0x01
Case 2:
StutterTime = 01h for minimum LDTSTP# assertion
duration of 1us in C3.
All Revs SP5100 PM_IO 0x8A = 0x90 Bit[7] - Enable Stutter Mode for C3
Bits[6:4] - VidFidTime = 001b for LDTSTP# assertion
duration of 2us in VID/FID change.
All Revs SP5100 PM_IO 0x89 = 0x10 This provides 16us delay before the assertion of LDTSTP#
when C3 is entered. The delay will allow USB DMA to go
on in a continuous manner.
All Revs SP5100 PM_IO 0x88 = 0x10 LdtStartTime = 10h for minimum LDTSTP# de-assertion
duration of 16us in StutterMode. This is to guarantee that
the HT link has been safely reconnected before it can be
disconnected again. If C3 pop-
up is enabled, the 16us also
serves as the minimum idle time before LDTSTP# can be
asserted again. This allows DMA to finish before the HT
link is disconnected.
The following two registers should be programmed only if the following is true:
MTC1E is enabled but FID/VID is not enabled or MTC1E is enabled but FID/VID is not enabled
All Revs SP5100 PM_IO 0x9A [2] = 1 Enables pop-up for C3
For internal bus mastering or BmReq# from the NB, the SB
will de-assert LDTSTP# (pop-up) to allow DMA traffic, then
assert LDTSTP# again after some idle time.
PM_IO 0x7C [0] = 1 Set this bit to 1 to allow wakeup from C3 if break event
happens before LDTSTOP# assertion.