Specifications

 2012 Advanced Micro Devices, Inc.
ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
AMD SP5100 Register Programming Requirements
Page 10
2 ACPI/SMBUS Controller (bus-0, dev-20, fun-0)
2.1 Enabling Legacy Interrupt
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0x62 [2] = 1 This bit enables legacy interrupt.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
x
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
2.2 Unblocked SMI Command Port
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0xAC [4] = 0 Set the bit to 0 to disable unblocked smi delivery from smi
command port so that smi from smi command port is gated
by EOS bit too.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
x
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
2.3 WakeIO Base Address
ASIC Rev Register Settings Function/Comment
All Revs SP5100 Smbus_PCI_config 0xF4 [15:0]
This register is the I/O base address used to generate the C-
state wake event by the processor. The BIOS should
program this register with the I/O base address for the
SP5100. The base address in the CPU should also be
programmed. The CPU can use it to generate an I/O write to
the SB to wake the system from the C-state.
SATA
USB
SMBUS
PATA
AC97
HD AUDIO
LPC
PCI
For register details refer to
the sections check-marked
in the SP5100 Register
Reference Guide
x
RTC
ACPI
PM REG
A-LINK
I/O REG
XIOAPIC
2.4 C-State and VID/FID Change
ASIC Rev Register Settings Function/Comment
All Revs SP5100
BIOS should not report ARB_DIS to OS if
C3 pop-up is enabled.
With C3 pop-up, ARB_DIS should not be set or cleared by
software.
PM_IO 0x9A [5] = 1 For system with dual core CPU, set this bit to 1 to
automatically clear BM_STS when the C3 state is being
initiated.